Wayne S. wrote discussing noise in CCD's pointing out that all process issues
being equally good,the main determinant of noise, is photodiode sensor area.
>>"There are only so many photons to catch, bigger pixels catch more photons."<<
I agree almost entirely with Wayne , but there are some second order effects
that **make modest differences** to noise performance, or if badly executed can
degrade inherent performance.
In general Wayne's comments apply, because the photo-diodes used inherently
have similar quantum efficiency.
That is, the the number of electrons generated per photon of light does not
vary a huge amount for silicon photo-detectors and thus photo-current scales
with area.
Also at very low light levels, light has inherently significant "quantum
noise", because there are only so many photons arriving at any time.
There is a modest quantum efficiecy change with light wavelength that depends
on depth of diffusion and voltage bias on photo-diode.
The intrinsict purity of the silicon used, does have some effect on dark
current and hence low light level noise.
The photodiode dark current (low light performance) is affected by chip
temperature, so power hungry chips are more noisey at low light levels.
This generally favours CMOS chips over CCD.
If the system noise is sensor limited (ideal good design), a 10C temperature
rise approximately doubles dark current leading to a 40% increase in noise
power.
Also increasing reverse bias on the photo-diode improves the quantum
efficiency, but it increases the dark current.
So biasing can make modest performance trade-offs of low-light performance and
speed vs bright performance and blue sensitivity .
The more wafer processing steps, the more chances for intoducing noise sources
from trapped contaminants in oxide etc.
So chip designs with more layers /processs steps will generally have more noise.
Noise of the readout amplifiers following the sensor should ideally be lower
than the sensor noise,
but as is illustrated by the success of niche companies like Nucore, who make
low noise post sensor amplifier chips, this is often not the case.
The switch + clocking scheme to shift charge from sensor capacitor to read
amplifier, adds noise in a CCD, this is due to capacitor mismatches and switch
charge injection.
Placing an amplifier transistor at each pixel can reduce clock noise at cost of
silicon area and linearity, which then can affect color mapping.
In general, both of these issues is likely to scale badly with high pixel count
and/or reduced sensor areas.
Performance improvements tend toward an assymtotic limit set by the physics of
photo-diodes, which is probably not too far distant from where we currently
are.
In theory the Foveon sensors might ultimately have a technology edge because
they use larger area pixels for a given chip size and don't throw away 66% of
the light in the "filters".
In reality the fact the Foveon color sensor seperation, results in broad
overlap, that then requires removal by subtraction, may make this less of an
advantage in practise.
Regards,
Tim Hughes
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